Antian Wang

Antian Wang

I am currently an Assistant Professor of Computer Engineering at Department of Electrical and Computer Engineering, Purdue University, Fort Wayne, Fort Wayne, IN, USA.

Publications

NNTesting: Neural Network Fault Attacks Detection Using Gradient-Based Test Vector Generation

Published in 2023 60th ACM/IEEE Design Automation Conference (DAC)., 2023

This paper is about the number 1. The number 2 is left for future work.

Recommended citation: Antian Wang, Bingyin Zhao, Weihang Tan, and Yingjie Lao. "NNTesting: Neural Network Fault Attacks Detection Using Gradient-Based Test Vector Generation." In 2023 60th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2023. .

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography

Published in IEEE Transactions on Computers., 2023

This paper propose a modular polynomial multiplication in power-of-two modulo using fast finite impulse response (FIR) filter architecture originally designed for digital signal processing.

Recommended citation: Weihang Tan, Antian Wang, Xinmiao Zhang, Yingjie Lao, and Keshab K. Parhi. "High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography." IEEE Transactions on Computers.. 2023.

Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography

Published in 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)., 2022

This paper propose a sampler design methodology that reuse the underlying computation resources within butterfly units.

Recommended citation: Antian Wang, Weihang Tan, Keshab K. Parhi, and Yingjie Lao. "Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography." In 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).. pp. 1-6. IEEE, 2022.

Pipelined high-throughput NTT architecture for lattice-based cryptography

Published in 2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)., 2021

This paper designs a NTT MDC based FPGA hardware accelerator for Lattice-based cryptography using folding.

Recommended citation: Weihang Tan, Antian Wang, Yingjie Lao, Xinmiao Zhang, and Keshab K. Parhi. "Pipelined high-throughput NTT architecture for lattice-based cryptography." In 2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST). pp. 1-4. IEEE, 2021.

NoPUF: A novel PUF design framework toward modeling attack resistant PUFs

Published in IEEE Transactions on Circuits and Systems I: Regular Papers., 2021

This paper propose a novel PUF design framework that select Challenge-Response Pairs that are still reliable under noisy PUF after reconfiguration.

Recommended citation: Antian Wang, Weihang Tan, Yuejiang Wen, and Yingjie Lao. "NoPUF: A novel PUF design framework toward modeling attack resistant PUFs." IEEE Transactions on Circuits and Systems I: Regular Papers.. 68, no. 6 (2021): 2508-2521.

High-speed modular multiplier for lattice-based cryptosystems

Published in IEEE Transactions on Circuits and Systems II: Express Briefs., 2021

This paper presents a modular multiplier for a custom prime with sparse sign-power-of-two property using a 2-decompose karatsuba algorithm to reduce the area consumption.

Recommended citation: Weihang Tan, Benjamin M. Case, Antian Wang, Shuhong Gao, and Yingjie Lao. "High-speed modular multiplier for lattice-based cryptosystems." IEEE Transactions on Circuits and Systems II: Express Briefs. 68, no. 8 (2021): 2927-2931.

Area-efficient pipelined VLSI architecture for polar decoder

Published in 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020

This paper discusses polar decoder adapted from optimized techniques used for Fast Fourier Transform to acchieve area-efficient architecture.

Recommended citation: Weihang Tan, Antian Wang, Yunhao Xu, and Yingjie Lao. "Area-efficient pipelined VLSI architecture for polar decoder." In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 352-357. IEEE, 2020.