Antian Wang

Antian Wang

I am currently an Assistant Professor of Computer Engineering at Department of Electrical and Computer Engineering, Purdue University, Fort Wayne, Fort Wayne, IN, USA.

Area-efficient pipelined VLSI architecture for polar decoder

Published in 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020

Recommended citation: Weihang Tan, Antian Wang, Yunhao Xu, and Yingjie Lao. "Area-efficient pipelined VLSI architecture for polar decoder." In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 352-357. IEEE, 2020.

This paper discusses polar decoder adapted from optimized techniques used for Fast Fourier Transform to acchieve area-efficient architecture.

Download paper here

Recommended citation: Weihang Tan, Antian Wang, Yunhao Xu, and Yingjie Lao. “Area-efficient pipelined VLSI architecture for polar decoder.” In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 352-357. IEEE, 2020.