High-speed modular multiplier for lattice-based cryptosystems
Published in IEEE Transactions on Circuits and Systems II: Express Briefs., 2021
Recommended citation: Weihang Tan, Benjamin M. Case, Antian Wang, Shuhong Gao, and Yingjie Lao. "High-speed modular multiplier for lattice-based cryptosystems." IEEE Transactions on Circuits and Systems II: Express Briefs. 68, no. 8 (2021): 2927-2931.
This paper presents a modular multiplier for a custom prime with sparse sign-power-of-two property using a 2-decompose karatsuba algorithm to reduce the area consumption.
Recommended citation: Weihang Tan, Benjamin M. Case, Antian Wang, Shuhong Gao, and Yingjie Lao. “High-speed modular multiplier for lattice-based cryptosystems.” IEEE Transactions on Circuits and Systems II: Express Briefs. 68, no. 8 (2021): 2927-2931.